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AC '97 2.2-COMPLIANT CODEC FEATURES S/PDIF Output, 20 Bits Data Format, Supporting 48 kHz and 44.1 kHz Sample Rates Integrated Stereo Headphone Amplifier Variable Sample Rate Audio External Audio Power-Down Control Greater than 90 dB Dynamic Range 16-Bit Stereo Full-Duplex Codec 20-Bit DAC Input Three Analog Line-Level Stereo Inputs for LINE-IN, AUX, and CD Mono Line-Level Phone Input Mono MIC Input with Built-In Programmable Preamp
AC `97 SoundMAX Codec AD1981A
High Quality CD Input with Ground Sense Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Lead LQFP Package ENHANCED FEATURES Built-in Digital Equalizer Function for Optimized Speaker Sound Full Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software-Programmed V REFOUT Output for Microphone Bias and External Power Amp Split Power Supplies: 3.3 V Digital and 5 V Analog Multiple Codec Configuration Options
(R)
FUNCTIONAL BLOCK DIAGRAM
VREF VREFOUT XTL_OUT XTL_IN ID1 ID0
AD1981A
MIC_IN AUX PHONE_IN CD_L CD_GND CD_R LINE_IN CD DIFF AMP
MIC PREAMP G VREF SELECTOR G XTAL OSCILLATOR LINK PORT/ ID SELECT
A/D SAMPLE RATE GENERATOR G G M M 16-BIT - A/D CONVERTER 16-BIT - A/D CONVERTER
PLL CLOCK GENERATOR
G G M HP_OUT_L HP M A M LINE_OUT_L M A SELECTOR GA GA M M M GA M M GA GA M M M GA GA GA
M
16-BIT - A/D CONVERTER 16-BIT - A/D CONVERTER 20-BIT - D/A CONVERTER 20-BIT - D/A CONVERTER
D/A SAMPLE RATE GENERATOR AC '97 SERIAL INTERFACE
M GA
SPKR EQ SPKR EQ
GA
EQ COEFF STORAGE
MONO_OUT
M
A
AC '97 CONTROL REGISTERS M ANALOG MUTE CONTROL LOGIC M SPDIF
LINE_OUT_R
M
A
HP_OUT_R
HP
M
A
JACK SENSE
EAPD
KEY: G = GAIN A = ATTENUATE M = MUTE
JS0
JS1
EAPD
SPDIF
SoundMAX is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AC '97 LINK SIGNALS
AD1981A-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature Digital Supply (DVDD) Analog Supply (VDD) Sample Rate (FS) Input Signal Analog Output Pass Band VIH VIL VIH (ID0, ID1) VIL (ID0, ID1)
25C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz 2.0 V 0.8 V 4.0 V 1.0 V
DAC Test Conditions Calibrated 0 dB Gain/Attenuation Relative to Full Scale 0 dB Input 10 k Output Load (LINE_OUT) 32 Output Load (HP_OUT) ADC Test Conditions Calibrated 0 dB Gain Input -3.0 dB Relative to Full Scale
Parameter ANALOG INPUT Input Voltage (RMS values assume sine-wave input) LINE_IN, AUX, CD, PHONE_IN MIC_IN with 20 dB gain MIC_IN with 0 dB gain Input Impedance1 Input Capacitance1 MASTER VOLUME Step Size (0 dB to -46.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range1 Step Size (0 dB to -46.5 dB); MONO_OUT Output Attenuation Range1 Step Size (0 dB to -46.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range1 Mute Attenuation of 0 dB Fundamental1 PROGRAMMABLE GAIN AMPLIFIER--ADC Step Size (0 dB to 22.5 dB) PGA Gain Range ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT Step Size (+12 dB to -34.5 dB): (All steps tested) MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC DIGITAL DECIMATION AND INTERPOLATION FILTERS Pass Band Pass Band Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation over Pass Band
1
Min
Typ
Max
Unit
1 2.83 0.1 0.283 1 2.83 20 5
7.5
Vrms Vp-p Vrms Vp-p Vrms Vp-p k pF
1.5 46.5 1.5 46.5 1.5 46.5 80 1.5 22.5
dB dB dB dB dB dB dB dB dB
90 90 1.5 46.5 0 0.4 x FS 0.6 x FS -74 16/FS 0 0.4 x FS 0.09 0.6 x FS
dB dB dB dB Hz dB Hz Hz dB s s
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AD1981A
SPECIFICATIONS
Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion (CCIF Method)1 ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error2 (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 DIGITAL-TO-ANALOG CONVERTERS Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT Dynamic Range (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion (CCIF Method)1 Gain Error (Actual Output Full-Scale Voltage Relative to Nominal Output Full-Scale) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)1 Total Audible Out-of-Band Energy (Measured from 0.6 x FS to 20 kHz)1 ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT and MONO_OUT Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance Full-Scale Output Voltage; HP_OUT (0 dB Gain) External Load Capacitance1 External Load Impedance1 VREF VREFOUT (selectable to 3.70 V nominal) VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range - Analog (AVDD) Power Supply Range - Digital (DVDD) Power Dissipation - 5 V/3.3 V Analog Supply Current - 5 V (AVDD) Digital Supply Current - 3.3 V(DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) CLOCK SPECIFICATIONS Input Clock Frequency Recommended Clock Duty Cycle REV. 0 -3-
1
Min
Typ 16 -84
Max
Unit Bits dB dB dB
80
85 85 -80 -100 -80 10 0.5 5
dB dB % dB mV Bits dB dB dB dB
20 -85 -75 85 90 -100 10 0.7 -80 -40 1 2.83 800 10 15 100 1 100 32 2.05 2.25 2.25 5 0.65 x DVDD 0.9 x DVDD -10 -10 4.65 3.15 2.45 5
% dB dB dB Vrms Vp-p k pF pF Vrms pF V V mA mV V V V V A A V V mW mA mA dB MHz %
0.35 x DVDD 0.1 x DVDD 10 10 5.25 3.45 555 78 50
40 24.576 50
40
60
AD1981A-SPECIFICATIONS
Parameter POWER-DOWN STATES (Fully Active) ADC DAC ADC + DAC Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Standby Headphone Standby
3
Set Bits (No Bits Value) PR0 PR1 PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 PR5, PR4, PR3, PR2, PR1, PR0 PR6
DVDD Typ 47 39 32 13 47 39 32 13 0 47
AVDD Typ 53 47 40 34 21 16 8 1 0 40
Unit mA mA mA mA mA mA mA mA mA mA
Parameter TIMING PARAMETERS (Guaranteed over Operating Temperature Range) RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter1 BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
NOTES 1 Guaranteed but not tested. 2 Measurement reflects main ADC. 3 Values presented with V REFOUT not loaded. Specifications subject to change without notice.
Symbol
Min
Typ
Max
Unit
tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
1.0 162.8 1.3 19.5 162.8 12.288 81.4 750 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4
ms ns ms ns MHz ns ps ns ns kHz ms ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns
32.56 32.56
48.84 48.84
5 5 2 2 2 2 2 2 2 2 0 15
6 6 6 6 6 6 6 6 1.0
25 15 50 15
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AD1981A
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted.)
Power Supplies Digital (DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V Analog (AVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6.0 V Input Current (except Supply Pins) . . . . . . . . . . . . . . . 10 mA Signals Pins Digital Input Voltage . . . . . . . . . . . . . -0.3 V to DVDD +0.3 V Analog Input Voltage . . . . . . . . . . . . -0.3 V to AVDD +0.3 V Ambient Temperature Range (Operating) . . . . . . . 0C to 70C
Ambient Temperature Rating (TQFP Package) TAMB = TCASE - ( PD CA ) TCASE = Case Temperature in C PD = Power Dissipation in W JA Thermal Resistance (Junction-to-Ambient) . . . 76.2C/W JC Thermal Resistance (Junction-to-Case) . . . . . . . 17C/W JA Thermal Resistance (Case-to-Ambient) . . . . . 52.2C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD1981AJST
*ST = Thin Quad Flatpack
Temperature Range 0C to 70C
Package Description 48-Lead LQFP
Package Option* ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1981A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD1981A
PIN CONFIGURATION
MONO_OUT
36 LINE_OUT_R 35 LINE_OUT_L 34 AVDD4 33 AVSS4 32 AFILT4 31 AFILT3 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF 26 AVSS1 25 AVDD1 13 14 15 16 17 18 19 20 21 22 23 24
HP_OUT_R
HP_OUT_L NC
SPDIF
AVDD3
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 XTL_IN 2
1
PIN 1 IDENTIFIER
XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 NC 12 NC = NO CONNECT
AD1981A
TOP VIEW (Not to Scale)
PHONE_IN
JS1
JS0
MIC_IN
AUX_L
AUX_R
CD_L
LINE_IN_L
CD_R
AVDD2
ID0 AVSS3
AVSS2
EAPD
ID1
NC
-6-
CD_GND_REF
LINE_IN_R
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AD1981A
PIN FUNCTION DESCRIPTIONS
Pin No. DIGITAL I/O 2 3 5 6 8 10 11 48 45 46 17 16 47 ANALOG I/O 13 14 15 18 19 20 21 23 24 35 36 37 39 41 27 28 29 30 31 32 1 4 7 9 25 26 33 34 38 40 43 44 NO CONNECTS 12 22 42
Mnemonic XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET SPDIF ID0 ID1 JS0 JS1 EAPD PHONE_IN AUX_L AUX_R CD_L CD_GND_REF CD_ R MIC_IN LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R VREF VREFOUT AFILT1 AFILT2 AFILT3 AFILT4 DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVSS4 AVDD4 AVDD2 AVSS2 AVDD3 AVSS3 NC NC NC
I/O I O I O/I O I I O I I I I O I I I I I I I I I O O O O O O O O O O O I I I I I I I I I I I I
Function Crystal Input (24.576 MHz) or External Clock Input Crystal Output AC-Link Serial Data Output, AD1981A Data Input Stream AC-Link Bit Clock Output (12.288 MHz) or Bit Clock Input if Secondary Mode Selected AC-Link Serial Data Input, AD1981A Data Output Stream AC-Link Frame Sync AC-Link Reset, AD1981A Master H/W Reset S/PDIF Output Chip Select Input 0 (Active Low) This pin can also be used as the chain input from a secondary Codec. Chip Select Input 1 (Active Low) JACK SENSE 0 Input JACK SENSE 1 Input External Amp Power-Down Control PHONE Input. Mono input from telephony subsystem speaker phone or handset. AUXILIARY Input Left Channel AUXILIARY Input Right Channel CD Audio Left Channel CD Audio Analog Ground Reference for Differential CD Input CD Audio Right Channel Microphone Input (Mono) Line In Left Channel Line In Right Channel Line Out (Front) Left Channel Line Out (Front) Right Channel Monaural Output to Telephony Subsystem Speakerphone Headphone Left Channel Output Headphone Right Channel Output Voltage Reference Filter Voltage Reference Output 5 mA Drive (Intended for Mic Bias and Power Amp Bias) Antialiasing Filter Capacitor--ADC Right Channel Antialiasing Filter Capacitor--ADC Left Channel Antialiasing Filter Capacitor--Mixer ADC Right Channel Antialiasing Filter Capacitor--Mixer ADC Left Channel Digital VDD 3.3 V Digital GND Digital GND Digital VDD 3.3 V Analog VDD 5.0 V Analog GND Analog GND Analog VDD 5.0 V Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND No Connect No Connect No Connect
CHIP SELECTS (These pins can also be used to select an external clock. See Table II.)
JACK SENSE AND EAPD
FILTER/REFERENCE (These signals are connected to resistors, capacitors, or specific voltages.)
POWER AND GROUND SIGNALS
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AD1981A
Indexed Control Registers
Reg 00h 02h 04h 06h 0Ch 0Eh 10h 12h 16h 18h 1Ah 1Ch 20h 26h 28h 2Ah 2Ch 32h 3Ah 60h 62h 64h 72h 74h 76h 7Ch 7Eh Name Reset Master Volume Headphones Volume Mono Volume Phone Volume Mic Volume Line In Volume CD Volume AUX Volume PCM Out Vol Record Select Record Gain General Purpose Power-Down Ctrl/Stat Ext'd Audio ID Ext'd Audio Stat/Ctrl (SR1) PCM L/R ADC Rate (SR0) SPDIF Control EQ CTRL EQ DATA Mixer ADC, Volume JACK SENSE Serial Configuration Misc Control Bits Vendor ID1 Vendor ID2 D15 X MM HPM MVM PHM MCM LM CM AM OM X IM X EAPD ID1 D14 SE4 X X X X X X X X X X X X PR6 ID0 SR14 SR14 X MAD D13 SE3 X X X X X X X X X X X X PR5 X X SR13 SR13 D12 SE2 LMV4 LHV4 X X X LLV4 LCV4 LAV4 LOV4 X X X PR4 X X SR12 SR12 D11 SE1 LMV3 LHV3 X X X LLV3 LCV3 LAV3 LOV3 X LIM3 X PR3 REV1 X SR11 SR11 D10 SE0 LMV2 LHV2 X X X LLV2 LCV2 LAV2 LOV2 LS2 LIM2 X PR2 REV0 SPCV SR10 SR10 CC6 X D9 ID9 LMV1 LHV1 X X X LLV1 LCV1 LAV1 LOV1 LS1 LIM1 X D8 ID8 LMV0 LHV0 X X X LLV0 LCV0 LAV0 LOV0 LS0 LIM0 X D7 ID7 RM* RM* X X X RM* RM* RM* RM* X RM* X X X SR7 SR7 CC3 SYM D6 ID6 X X X X M20 X X X X X D5 ID5 X X X X X X X X X X X X X DSA1 SR5 SR5 CC1 BCA5 D4 ID4 RMV4 RHV4 MV4 PHV4 MCV4 RLV4 RCV4 RAV4 ROV4 X X X X DSA0 SR4 SR4 CC0 BCA4 CFD4 X JS0 MD INTS MAD ST S4 REV4 D3 ID3 RMV3 RHV3 MV2 PHV3 MCV3 RLV3 RCV3 RAV3 ROV3 X RIM3 X REF X SR3 SR3 PRE BCA3 CFD3 RMG3 JS1 ST X D2 ID2 RMV2 RHV2 MV2 PHV2 MCV2 RLV2 RCV2 RAV2 ROV2 RS2 RIM2 X ANL SPDIF SPDIF SR2 SR2 COPY BCA2 CFD2 RMG2 JS0 ST SPAL D1 D0 Default 0090h 8000h 8000h 8000h 8008h 8008h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 000Xh X605h 0000h BB80h BB80h 2000h 8080h 0000h 8000h 0000h
ID1 ID0 RMV1 RMV0 RHV1 MV1 PHV1 RLV1 RCV1 RHV0 MV0 PHV0 RLV0 RCV0
MCV1 MCV0
RAV1 RAV0 ROV1 ROV0 RS1 RIM1 X DAC X X SR1 SR1 /AUD BCA1 CFD1 RS0 RIM0 X ADC VRA VRA SR0 SR0 PRO BCA0 CFD0
X LPBK X X X X SR6 SR6 CC2 CHS
PR1 PR0 AMAP X X SR9 SR9 CC5 X X SR8 SR8 CC4 X
VFORCE X
SPSA1 SPSA0 X
PCM Front DAC Rate SR15 SR15 V EQM CFD15 MXM X SLOT 16 DACZ F7 T7
SPSR1 SPSR0 L X X CFD12 X JS MT2 REGM 0 X F4 T4 X
LBEN CFD14 CFD13 X X X X
CFD11 CFD10 CFD9 LMG3 JS MT1 X DAM F3 T3 LMG2 JS MT0 X X F2 T2
CFD8 CFD7 LMG1 LMG0 RM* JS1 JS0 JS1 EQB EQB TMR X CHEN X X
CFD6 CFD5 X JS0 TMR X MAD PD X JS1 MD X X
RMG1 RMG0 JS1 JS0 INT INT
REGM REGM 2 1 X M SPLT F6 T6 F5 T5
SPDZ SPLNK 7001h 0000h 4144h 5372h
FMXE X F1 T1 F0 T0
VREFH VREFD MBG1 MBG0 S3 REV3 S2 REV2 S1 REV1 S0 REV0
S7 S6 S5 REV7 REV6 REV5
NOTES All registers not shown. Bits containing an X are assumed to be reserved. Odd registers are reserved, not aliased. Reserved registers should not be written to. Zeros should be written to bits containing an X. *For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT Bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
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AD1981A
Reset (Index 00h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h
Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement.
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981A based on the following: Bit ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated Mic PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1981A 0 0 0 0 1 0 0 1 0 0
SE[4:0] Stereo Enhancement: The AD1981A does not provide hardware 3D stereo enhancement (all bits are zeros).
Master Volume Register (Index 02h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 02h Master Volume MM X X LMV4 LMV3 LMV2 LMV1 LMV0 RM* X X RMV4 RMV3 RMV2 RMV1 RMV0 8000h
* For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
This register controls the line_out volume controls for both stereo channels and mute bit. Each volume subregister contains 5 bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC `97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 bits are set to "1," their respective lower five volume bits are automatically set to "1" by the Codec logic. On readback, all lower 5 bits will read ones whenever these bits are set to "1." RMV[4:0] RM LMV[4:0] MM Right Master Volume Control: The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -46.5 dB. Right Channel Mute: Once enabled by the MSPLT Bit in Register 76h, this bit mutes the right channel separately from the MM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left Master Volume Control: The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -46.5 dB. Master Volume Mute: When this bit is set to "1," both L/R channels are muted, unless the MSPLT bit in Register 76h is set to "1," in which case this mute bit will only affect the left channel.
MM 0 0 0 0 1
xMV5...xMV0 WRITE READBACK 00 0000 00 1111 01 1111 1x xxxx xx xxxx 00 0000 00 1111 01 1111 01 1111 xx xxxx
Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain
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AD1981A
Headphones Volume Register (Index 04h) 1
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 04h Headphones Volume HPM X X LHV4 LHV3 LHV2 LHV1 LHV0 RM2 X X RHV4 RHV3 RHV2 RHV1 RHV0 8000h
NOTES 1 This register controls the headphone volume controls for both stereo channels and mute bit. Each volume subregister contains 5 bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC `97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 Bits are set to "1, " their respective lower five volume bits are automatically set to "1" by the CODEC logic. On readback, all lower 5 bits will read ones when ever these bits are set to "1." 2 For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
RHV [4:0] RM LHV [4:0] HPM
Right Headphone Volume Control: The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -46.5 dB. Right Channel Mute: Once enabled by the MSPLT Bit in Register 76h, this bit mutes the right channel separately from the HPM Bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left Headphone Volume Control: The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -46.5 dB. Headphones Volume Mute: When this bit is set to "1," both L/R channels are muted, unless the MSPLT Bit in Register 76h is set to "1," in which case, this mute bit will only affect the left channel.
HPM 0 0 0 0 1
xHV5...xHV0 Function WRITE READBACK 00 0000 00 1111 01 1111 1x xxxx xx xxxx 00 0000 00 1111 01 1111 01 1111 xx xxxx
Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain
Mono Volume (Index 06h) *
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 06h Mono Volume MVM X X X X X X X X X X MV4 MV3 MV2 MV1 MV0 8000h
*This register controls the headphone volume controls for both stereo channels and mute bit. Each volume subregister contains 5 bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC `97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D13 Bits are set to "1, " their respective lower five volume bits are automatically set to "1" by the CODEC logic. On readback, all lower 5 bits will read ones when ever these bits are set to "1."
MV[4:0] MVM
Mono Volume Control: The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -46.5 dB. Mono Volume Mute: When this bit is set to "1," the channel is muted. xMV5...xMV0 WRITE READBACK 00 0000 00 1111 01 1111 1x xxxx xx xxxx 00 0000 00 1111 01 1111 01 1111 xx xxxx
MVM 0 0 0 0 1
Function 0 dB Gain -22.5 dB Gain -46.5 dB Gain -46.5 dB Gain - dB Gain
Phone Volume (Index 0Ch)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Phone Volume PHM X 0Ch X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 8008h
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AD1981A
PHV[4:0] PHM Phone Volume: Allows setting the phone volume attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB with mute bit enabled. Phone Mute: When this bit is set to "1," the phone channel is muted.
Mic Volume (Index 0Eh)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0Eh Mic Volume MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h
MCV[4:0] M20 MIC Volume Gain: Allows setting the mic volume attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB with mute enabled. MIC Gain Boost: This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal gain boost by default is 20 dB; however, bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register (76h) allow changing the gain boost to 10 dB or 30 dB if necessary. 0 = Disabled; Gain = 0 dB 1 = Enabled; Default Gain = 20 dB (see Register 76h, bits D0, D1) MIC Mute: When this bit is set to "1," the MIC channel is muted.
Line In Volume (Index 10h)
MCM
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 10h Line In Volume LM X X LLV4 LLV3 LLV2 LLV1 LLV0 RM* X X RLV4 RLV3 RLV2 RLV1 RLV0 8808h
*For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
RLV[4:0] RM LLV[4:0] LM
Line In Volume Right: Allows setting the line in right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute: Once enabled by the MSPLT Bit in Register 76h, this bit mutes the right channel separately from the LM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Line In Volume Left: Allows setting the line in left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Mute: When this bit is set to "1," both L/R channels are muted unless the MSPLT Bit in Register 76h is set to "1," in which case this mute bit will only affect the left channel.
CD Volume (Index 12h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 12h CD Volume CM X X LCV4 LCV3 LCV2 LCV1 LCV0 RM* X X RCV4 RCV3 RCV2 RCV1 RCV0 8808h
*For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
RCV[4:0] RM LCV[4:0] CM
Right CD Volume: Allows setting the CD right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute: Once enabled by the MSPLT Bit in Register 76h, this bit mutes the right channel separately from the CM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left CD Volume: Allows setting the CD left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute: When this bit is set to "1," both L/R channels are muted, unless the MSPLT Bit in Register 76h is set to "1," in which case, this mute bit will only affect the left channel.
REV. 0
-11-
AD1981A
AUX Volume (Index 16h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 16h AUX Volume AM X X LAV4 LAV3 LAV2 LAV1 LAV0 RM* X X RAV4 RAV3 RAV2 RAV1 RAV0 8808h
*For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
RAV[4:0] RM LAV[4:0] AM
Right AUX Volume: Allows setting the AUX right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute: Once enabled by the MSPLT Bit in Register 76h, this bit mutes the right channel separately from the AM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left AUX Volume: Allows setting the AUX left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. AUX Mute: When this bit is set to "1," both L/R channels are muted unless the MSPLT Bit in Register 76h is set to "1," in which case this mute bit will only affect the left channel.
PCM Out Volume (Index 18h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 18h PCM Out Vol OM X X LOV4 LOV3 LOV2 LOV1 LOV0 RM* X X ROV4 ROV3 ROV2 ROV1 ROV0 8808h
*For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
ROV[4:0] RM LOV[4:0] OM
Right PCM Out Volume: Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Right Channel Mute: Once enabled by the MSPLT Bit in Register 76h, this bit mutes the right channel separately from the OM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left PCM Out Volume: Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute: When this bit is set to "1," both L/R channels are muted unless the MSPLT Bit in Register 76h is set to "1," in which case this mute bit will only affect the left channel.
Volume Table (Index 0Ch to 18h)
Mute 0 0 0 1
x4...x0 00000 01000 11111 xxxxx
Function +12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain
Record Select Control Register (Index 1Ah)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1Ah Record Select X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0000h
RS[2:0] LS[2:0]
NOTES Used to select the record source independently for right and left. See table for legend. The default value is 0000h, which corresponds to MIC in.
Right Record Select Left Record Select
-12-
REV. 0
AD1981A
RS1...RS0 0 1 2 3 4 5 6 7 Right Record Source MIC CD_R Muted AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN
LS1...LS0 0 1 2 3 4 5 6 7
Left Record Source MIC CD_L Muted AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN
Record Gain (Index 1Ch)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 RM* X X X RIM3 RIM2 RIM1 RIM0 8000h
*For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
RIM[3:0] RM LIM[3:0] IM
Right Input Mixer Gain Control: Each LSB represents 1.5 dB, 0000 = 0 dB, and the range is 0 dB to 22.5 dB. Right Channel Mute: Once enabled by the MSPLT Bit in Register 76h, this bit mutes the right channel separately from the IM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left Input Mixer Gain Control: Each LSB represents 1.5 dB, 0000 = 0 dB, and the range is 0 dB to 22.5 dB. Input Mute: When this bit is set to "1," both L/R channels are muted unless the MSPLT Bit in Register 76h is set to "1," in which case this mute bit will only affect the left channel.
IM 0 0 1
xIM3...xIM0 1111 0000 xxxxx
Function +22.5 dB Gain 0 dB Gain - dB Gain
General Purpose Register (Index 20h)*
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 20h General Purpose X X X X X X X X LPBK X X X X X X X 0000h
*This register should be read before writing to generate a mask for only the bit(s) that need to be changed.
LPBK
Loop-Back Control: ADC/DAC digital loop-back mode
REV. 0
-13-
AD1981A
Power-Down Control/Status Register (Index 26h)
Reg Num Name Power-Down Cntrl/Stat 26h
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh
NOTES The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1981A subsections. If the bit is a "1" then that subsection is "ready." Ready is defined as the subsection able to perform in its nominal state.
ADC DAC ANL REF PR[6:0]
ADC sections ready to transmit data DAC sections ready to accept data Analog amplifiers, attenuators, and mixers ready Voltage references, VREF and VREFOUT up to nominal level CODEC Power-Down Modes. The first 3 bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the AC Link are powered down. The reference and mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master CODEC's PR5 and PR4 bits control the slave CODEC. PR5 is also effective in the slave CODEC if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. External Audio Power-Down Control: Controls the state of the EAPD Pin EAPD = 0 sets the EAPD Pin low, enabling an external power amplifier (reset default). EAPD = 1 sets the EAPD Pin high, shutting the external power amplifier off. Power-Down State ADCs and Input Mux Power-Down DACs Power-Down Analog Mixer Power-Down (VREF and VREFOUT on) Analog Mixer Power-Down (VREF and VREFOUT off) AC-Link Interface Power-Down Internal Clocks Disabled ADC and DAC Power Down VREF Standby Mode Total Power-Down Headphone Amp Power in Standby Set Bits PR0 PR1 PR1, PR2 PR0, PR1, PR3 PR4 PR0, PR1, PR4, PR5 PR0, PR1 PR0, PR1, PR2, PR4, PR5 PR0, PR1, PR2, PR3, PR4, PR5 PR6
EAPD
Extended Audio ID Register (Index 28h)
REG NAME 28h Ext'd Audio ID
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default ID1 ID0 X X REV1 REV0 AMAP X X X DSA1 DSA0 X SPDIF X VRA X605h
The extended audio ID register identifies which extended audio features are supported. A non-zero extended audio ID value indicates one or more of the extended audio features are supported.
-14-
REV. 0
AD1981A
VRA SPDIF DSA[1:0] Variable Rate PCM Audio Support: (read-only) This bit returns a "1" when read to indicate that variable rate PCM audio is supported. SPDIF Support: (read-only) This bit returns a "1" when read to indicate that SPDIF transmitter is supported (IEC958). DAC Slot Assignments: (read/write) (reset default = 00) 00 DACs 1, 2 = 3 and 4 01 DACs 1, 2 = 7 and 8 10 DACs 1, 2 = 6 and 9 11 DACs 1, 2 = 10 and 11 Slot DAC mappings based on Codec ID: (read only) This bit returns a "1" when read to indicate that slot/DAC mappings based on Codec ID is supported. REV[1, 0] = 01 indicates Codec is AC '97 revision 2.2-compliant (read-only). Indicates Codec Configuration: (read-only) 00 = Primary 01, 10, 11 = Secondary
AMAP REV[1:0] ID[1:0]
Extended Audio Status and Control Register (Index 2Ah)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 2Ah Ext'd Audio Stat/Ctrl VFORCE X X X X SPCV X X X X SPSA1 SPSA0 X SPDIF X VRA 0000h
*The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
VRA
Variable Rate Audio: (read/write) VRA = 0, sets fixed sample rate audio at 48 KHz (reset default). VRA = 1, enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). SPDIF Transmitter Subsystem Enable/Disable Bit: (read/write) SPDIF = 1 enables the SPDIF transmitter. SPDIF = 0 disables the SPDIF transmitter (default). This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set high if the SPDIF pin (48) is pulled down at power-up enabling the Codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. SPDIF Slot Assignment Bits: (read/write) These bits control the SPDIF slot assignment and respective defaults, depending on the Codec ID configuration. SPDIF Configuration Valid: (read-only) Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF-enable bit status. SPCV = 0 indicates current SPDIF configuration {SPSA, SPSR, DAC slot rate, DRS} is not valid (not supported). SPCV = 1 indicates current SPDIF configuration {SPSA, SPSR, DAC slot rate, DRS} is valid (supported). Validity Force Bit: (reset default = 0) When asserted, this bit forces the SPDIF stream "Validity" flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the "V" bit (D15) in Register 3Ah (SPDIF control register). VFORCE = 0 and "V" = 0; The "Validity" bit is managed by the Codec error detection logic. VFORCE = 0 and "V" = 1; The "Validity" bit is forced high, indicating subframe data is invalid. VFORCE = 1 and "V" = 0; The "Validity" bit is forced low, indicating subframe data is valid. VFORCE = 1 and "V" = 1; The "Validity" bit is forced high, indicating subframe data is invalid.
SPDIF
SPSA[1:0] SPCV
VFORCE
REV. 0
-15-
AD1981A
AC '97 2.2 AMAP-Compliant Default SPDIF Slot Assignments
CODEC ID 00 00 00 01 01 10 10 11
Function 2-Ch Primary w/SPDIF 4-Ch Primary w/SPDIF 6-Ch Primary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF +4-Ch Secondary w/SPDIF +2-Ch Secondary w/SPDIF
SPSA = 00 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4 3 and 4
SPSA = 01 7 and 8 [default] 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8 7 and 8
SPSA = 10 6 and 9 6 and 9 [default] 6 and 9 6 and 9 [default] 6 and 9 6 and 9 [default] 6 and 9 6 and 9
SPSA = 11 10 and 11 10 and 11 10 and 11 [default] 10 and 11 [default] 10 and 11 [default] 10 and 11 [default]
PCM Front DAC Rate Register (Index 2Ch)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 2Ch PCM Front DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
*This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.
SR[15:0]
Sample Rate: The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If "0" is written to VRA, then the sample rate is reset to 48k.
PCM ADC Rate Register (Index 32h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 32h PCM L/R ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.
SR[15:0]
Sample Rate: The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If "0" is written to VRA, then the sample rate is reset to 48k.
SPDIF Control Register (Index 3Ah)
Reg. Num. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 3Ah SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h
*Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in Register 2Ah is "0"). This ensures that control and status information start up correctly at the beginning of SPDIF transmission.
PRO /AUD COPY PRE CC[6:0] L SPSR[1:0]
Professional: "1" indicates professional use of channel status, "0" indicates consumer. Non-Audio: "1" indicates data is non-PCM format, "0" data is PCM. Copyright: "1" indicates copyright is asserted, "0" copyright is not asserted. Pre-Emphasis: "1" indicates filter pre-emphasis is 50/15 msec, "0" pre-emphasis is none. Category Code: Programmed according to IEC standards, or as appropriate. Generation Level: Programmed according to IEC standards, or as appropriate. SPDIF Transmit Sample Rate: SPSR[1:0] = "00" Transmit Sample Rate = 44.1 kHz SPSR[1:0] = "01" Reserved SPSR[1:0] = "10" Transmit Sample Rate = 48 kHz (Reset Default) SPSR[1:0] = "11" Not Supported Validity: This bit affects the "Validity" flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = 1 Each SPDIF subframe (L + R) has Bit 28 set to "1." This tags both samples as invalid. V = 0 Each SPDIF subframe (L + R) has Bit 28 set to "0" for valid data and "1" for invalid data (error condition). Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext'd Audio Stat/Ctrl) will force the "Validity" flag low, marking both samples as valid.
V
-16-
REV. 0
AD1981A
EQ Control Register (Index 60h)
Reg. Num. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 60h EQCTRL EQM MAD LBEN X X X X X X SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 8080h
*Register 60h is a read/write register that controls the equalizer functionality and data setup. The register also contains the biquad and coefficient address pointer, which is used in conjunction with the EQ data register (78h) to set up the equalizer coefficients.
The reset default disables the equalizer function until the coefficients can be properly set up by the software and sets the Symmetry Bit to allow equal coefficients for left and right channels. BCA[5,0] Biquad and Coefficient Address Pointer: biquad 0 coef a0 BCA[5,0] = 011011 biquad 0 coef a1 BCA[5,0] = 011010 biquad 0 coef a2 BCA[5,0] = 011001 biquad 0 coef b1 BCA[5,0] = 011101 biquad 0 coef b2 BCA[5,0] = 011100 biquad 1 coef a0 BCA[5,0] = 100000 biquad 1 coef a1 BCA[5,0] = 011111 biquad 1 coef a2 BCA[5,0] = 011110 biquad 1 coef b1 BCA[5,0] = 100010 biquad 1 coef b2 BCA[5,0] = 100001 biquad 2 coef a0 BCA[5,0] = 100101 biquad 2 coef a1 BCA[5,0] = 100100 biquad 2 coef a2 BCA[5,0] = 100011 biquad 2 coef b1 BCA[5,0] = 100111 biquad 2 coef b2 BCA[5,0] = 100110 biquad 3 coef a0 BCA[5,0] = 101010 biquad 3 coef a1 BCA[5,0] = 101001 biquad 3 coef a2 BCA[5,0] = 101000 biquad 3 coef b1 BCA[5,0] = 101100 biquad 3 coef b2 BCA[5,0] = 101011 biquad 4 coef a0 BCA[5,0] = 101111 biquad 4 coef a1 BCA[5,0] = 101110 biquad 4 coef a2 BCA[5,0] = 101101 biquad 4 coef b1 BCA[5,0] = 110001 biquad 4 coef b2 BCA[5,0] = 110000 biquad 5 coef a0 BCA[5,0] = 110100 biquad 5 coef a1 BCA[5,0] = 110011 biquad 5 coef a2 BCA[5,0] = 110010 biquad 5 coef b1 BCA[5,0] = 110110 biquad 5 coef b2 BCA[5,0] = 110101 biquad 6 coef a0 BCA[5,0] = 111001 biquad 6 coef a1 BCA[5,0] = 111000 biquad 6 coef a2 BCA[5,0] = 110111 biquad 6 coef b1 BCA[5,0] = 111011 biquad 6 coef b2 BCA[5,0] = 111010
REV. 0
-17-
AD1981A
CHS Channel Select: CHS = 0 Selects Left Channel Coefficients Data Block CHS = 1 Selects Right Channel Coefficients Data Block Symmetry: When set to "1," this bit indicates that the left and right channel coefficients are equal. This shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and set up (the right channel coefficients are fetched from the left channel memory). Mixer ADC Loop-Back Enable: Enables mixer ADC data to be summed into PCM stream. 0 = No Loop-Back allowed (default) 1 = Enable Loop-Back Equalizer Mute: When set to "1," this bit disables the equalizer function (allows all data pass-through). The reset default sets this bit to "1," disabling the equalizer function until the biquad coefficients can be properly set.
SYM
MAD LBEN EQM
EQ Data Register (Index 62h)
Reg. Num. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed by the BCA bits in the EQ CNTRL Register (60h). Data will only be written to memory if the EQM Bit (Register 60h Bit 15) is asserted. DACs should be powered down when new EQ coefficients are being added.
CFD[15:0]
Coefficient Data: The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is the MSB, and the CFD0 bit is the LSB.
Mixer ADC, Input Gain Register (Index 64h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 64h Mixer Volume MXM X X X LMG3 LMG2 LMG1 LMG0 RM* X X X RMG3 RMG2 RMG1 RMG0 8000h
*For AC `97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit in Register 76h. The MSPLT bit enables separate mute bits for the left and right channels. If MSPLT is not set, RM bit has no effect.
RMG[3:0] RM LMG[3:0] MXM
Right Mixer Gain Control: This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of +22.5 dB. The least significant bit represents 1.5 dB. Right Channel Mute: Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately from the IM bit. Otherwise, this bit will always read "0" and will have no effect when set to "1." Left Mixer Gain Control: This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of +22.5 dB. The least significant bit represents 1.5 dB. Mixer Gain Mute: 0 = Unmuted, 1 = Muted or - dB gain. MXM 0 0 1 xMG3...xMG0 1111 0000 xxxxx Function +22.5 dB gain 0 dB gain - dB gain
Jack Sense/Audio Interrupt/Status Register (Index 72h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 72h JACK SENSE X X X JS JS JS JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 0000h MT2 MT1 MT0 EQB EQB TMR TMR MD MD ST ST INT INT
All register bits are read/write except for JS0ST and JS1ST, which are read only.
-18-
REV. 0
AD1981A
JS0INT Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR, should clear this bit by writing a "0" to it. Note that the interrupt to the system is actually an OR combination of this bit and JS1INT. Also note that the actual interrupt implementation is selected by the INTS Bit (Reg 74h). It is also possible to generate a software system interrupt by writing a "1" to this bit. Indicates Pin JS1 has generated an interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR should clear this bit by writing a "0" to it. See JS0INT description above for additional details. JS0 STATE: This bit always reports the logic state of JS0 Pin. JS1 STATE: This bit always reports the logic state of JS1 Pin. JS0 MODE: This bit selects the operation mode for the JS0 Pin. 0 = Jack Sense Mode (Default) 1 = Interrupt Mode JS1 MODE: This bit selects the operation mode for the JS1 Pin. 0 = Jack Sense Mode (Default) 1 = Interrupt Mode JS0 Timer Enable: If this bit is set to a "1," JS0 must be high for greater than 250 ms to be recognized. JS1 Timer Enable: If this bit is set to a "1," JS1 must be high for greater than 250 ms to be recognized. JS0 EQ Bypass Enable: This bit enables JS0 to control the EQ bypass. When this bit is set to "1," JS0 = 1 will cause the EQ to be bypassed. JS1 EQ Bypass Enable: This bit enables JS1 to control the EQ bypass. When this bit is set to "1," JS1 = 1 will cause the EQ to be bypassed. JS Mute Enable Selector: These 3 bits select and enable the Jack Sense muting action (see Table I).
JS1INT
JS0ST JS1ST JS0MD
JS1MD
JS0TMR JS1TMR JS0EQB JS1EQB JSMT[2,0]
REV. 0
-19-
AD1981A
Table I. Jack Sense Mute Table - JSMT [2:0]
REF JS1 HEADPHONE 0 OUT (0) 1 OUT (0) 2 IN 3 IN (1) (1) JS0 LINE OUT OUT (0) IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) OUT (0) JSMT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 JSMT1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 JSMT0 H.P. OUT LINE OUT MONO OUT NOTES
0 ACTIVE ACTIVE ACTIVE JS0 and JS1 0 ACTIVE ACTIVE ACTIVE Ignored 0 ACTIVE ACTIVE ACTIVE 0 ACTIVE ACTIVE ACTIVE 1 FMUTE 1 FMUTE FMUTE ACTIVE JS0 no mute action, ACTIVE ACTIVE ACTIVE JS0 no mute action, FMUTE FMUTE ** ** ** ** ACTIVE JS0 mutes Mono, JS1 no mute action ACTIVE ACTIVE JS0 mutes Mono, JS1 mutes Line_out ACTIVE FMUTE ACTIVE JS0 mutes Mono, JS1 mutes Mono and Line_out ** RESERVED FMUTE FMUTE ** ** ** ** ** RESERVED Line_out ACTIVE ACTIVE JS1 mutes Line_out
4 OUT (0) 5 OUT (0) 6 IN 7 IN (1) (1)
1 ACTIVE FMUTE 1 ACTIVE FMUTE 0 FMUTE 0 FMUTE FMUTE
8 OUT (0) 9 OUT (0) 10 IN 11 IN (1) (1)
ACTIVE ACTIVE JS1 mutes Mono and
0 ACTIVE FMUTE 0 ACTIVE FMUTE 1 ** 1 ** 1 ** 1 ** 0 FMUTE 0 FMUTE ** ** ** ** FMUTE
12 OUT (0) 13 OUT (0) 14 IN 15 IN (1) (1)
16 OUT (0) 17 OUT (0) 18 IN 19 IN (1) (1)
ACTIVE FMUTE
0 ACTIVE FMUTE 1 FMUTE 1 FMUTE FMUTE
0 ACTIVE ACTIVE FMUTE ACTIVE FMUTE
20 OUT (0) 21 OUT (0) 22 IN 23 IN (1) (1)
1 ACTIVE FMUTE 1 ACTIVE FMUTE 0 FMUTE 0 FMUTE FMUTE
24 OUT (0) 25 OUT (0) 26 IN 27 IN (1) (1)
ACTIVE FMUTE
0 ACTIVE FMUTE 0 ACTIVE FMUTE 1 ** 1 ** 1 ** 1 ** ** ** ** **
28 OUT (0) 29 OUT (0) 30 IN 31 IN (1) (1)
FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective volume register setting. OUT = Nothing plugged into the jack and, therefore, the JS status is low (via the load resistor pull-down). IN = Jack has plug inserted and therefore the JS status is high (via the CODEC JS internal pull-up).
Serial Configuration (Index 74h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 74h Serial Configuration SLOT16 REGM2 REGM1 REGM0 X X X CHEN X X X INTS X SPAL SPDZ SPLNK 7001h
This register is not reset when the reset register (Register 00h) is written.
SPLNK
SPDIF LINK: This bit enables the SPDIF to link with the DAC for data requesting. 0 = SPDIF and DAC are not linked. 1 = SPDIF and DAC are linked and receive same data requests (reset default). SPDIF DACZ: 0 = Repeat last sample out the SPDIF stream if FIFO underruns (reset default). 1 = Forces "midscale" sample out the SPDIF stream if FIFO underruns. SPDIF ADC Loop Around: 0 = SPDIF transmitter is connected to the AC-LINK stream (reset default). 1 = SPDIF transmitter is connected to the digital ADC stream, not the AC-LINK. INTERRUPT MODE SELECT: This bits selects the JS interrupt implementation path. 0 = Bit 0 SLOT 12 (Modem Interrupt) 1 = Slot 6 Valid Bit (MIC ADC Interrupt) Chain Enable: This bit enables chaining of a slave CODEC SDATA_IN stream into the ID0 Pin (45). 0 = Disable Chaining (Reset Default) 1 = Enable Chaining into ID0 Pin -20- REV. 0
SPDZ
SPAL
INTS
CHEN
AD1981A
REGM0 REGM1 REGM2 SLOT16 Master Codec Register Mask Slave 1 Codec Register Mask Slave 2 Codec Register Mask Enable 16-Bit Slot Mode. SLOT16 makes all AC link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for DSP serial port interfacing.
Miscellaneous Control Bits (Index 76h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 76h Misc Control Bits DACZ X MSPLT X DAM X FMXE X X MADPD X MADST VREFH VREFD MBG1 MBG0 0000h
MBG[1:0]
MIC Boost Gain Change Register: These two bits allow changing the MIC preamp gain from the nominal 20 dB gain. Note: This gain setting only takes effect while Bit D6 (M20) on the MIC Volume Register (0Eh) is set to 1. Otherwise the MIC boost block has a gain of 0 dB. 00 = 20 dB Gain (Reset Default) 01 = 10 dB Gain 10 = 30 dB Gain 11 = Reserved VREFOUT Disable: Disables VREFOUT placing it into High Zout mode. Note that this bit overrides the VREFH bit selection (see below). 0 = VREFOUT Pin Is Driven by the Internal Reference (Reset Default) 1 = VREFOUT Pin Is Placed into High Zout Mode VREFOUT High: Changes VREFOUT from 2.25 V to 3.70 V for MIC bias applications. 0 = VREFOUT Pin Is set to 2.25 V Output (Reset Default) 1 = VREFOUT Pin Is set to 3.70 V Output Mixer ADC Status Bit: Indicates status of mixer digitizing ADC (L/R channels) 0 = Mixer ADC Not Ready 1 = Mixer ADC Is Ready Mixer ADC Power-Down: Controls power-down for mixer digitizing ADC. 0 = Mixer ADC Is Powered-On (Default) 1 = Mixer ADC Is Powered-Down Front DAC into Mixer Enable: Controls the Front (main) DAC to Mixer mute switches. 0 = Front DAC Outputs Are Allowed to Sum into the Mixer (Reset Default) 1 = Front DAC Outputs Are Muted into the Mixer (Blocked) Digital Audio Mode: PCM DAC outputs bypass the analog mixer and are sent directly to the Codec output. Mute Split: Allows separate mute control bits for master, Headphone, LINE_IN, CD, AUX, and PCM volume control Registers as well as Record Gain Register and mixer ADC volume. 0 = Both Left and Right Channel Mutes Are Controlled by Bit 15 in the Respective Registers (Reset Default) 1 = Bit 15 Affects Only the Left Channel Mute and Bit 7 Affects Only the Right Channel Mute DAC Zero-Fill: (versus repeat) if DAC is starved for data. 0 = When DAC Is Filled with Repeat Data 1 = When DAC Is Filled with Zeros (Reset Default)
Vendor ID Registers (Index 7Ch)
VREFD
VREFH
MADST
MADPD
FMXE
DAM MSPLT
DACZ
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h
S[7:0] This register is ASCII encoded to `A' F[7:0] This register is ASCII encoded to `D'
REV. 0
-21-
AD1981A
Vendor ID Registers (Index 7Eh)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5372h
T[7:0] This register is ASCII encoded to `S' REV[7:0] Vendor-specific revision number: The AD1981A assigns 71h to this field.
Table II. Codec ID and External Clock Selection
ID1 1 1 0 0
IDO 1 0 1 0
CODEC ID (00) PRIMARY (01) SECONDARY (00) PRIMARY (00) PRIMARY
CODEC CLOCKING SOURCE 24.576 MHz (Local Xtal or External into XTL_IN) 12.288 MHz (External into Bit_Clk) 48.000 MHz (External into XTL_IN) 14.31818 MHz (External into XTL_IN)
Note that the ID# Pins have weak internal pull-ups and are inverted internally.
-22-
REV. 0
AD1981A
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches)
48-Lead Thin Plastic Quad (LQFP) (ST-48)
1.60 (0.0630) MAX GAGE PLANE 0.25 (0.0098) 0.75 (0.0295) 0.60 (0.0236) 0.45 (0.0177) 9.00 (0.3543) BSC SQ
36 37 25 24
SEATING PLANE
TOP VIEW
(PINS DOWN)
VIEW A
48 13 12
7.00 (0.2756) BSC SQ
1
PIN 1 INDICATOR
0.50 (0.0197) 0.27 (0.0106) BSC 0.22 (0.0087)
0.17 (0.0067)
1.45 (0.0571) 1.40 (0.0551) 1.35 (0.0531) 0.20 (0.0079) 0.09 (0.0035) 7 3.5 0 COPLANARITY 0.08 (0.0031) MAX
0.15 (0.0059) 0.05 (0.0020)
VIEW A
ROTATED 90 CCW
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-026-BBC
REV. 0
-23-
-24-
C02650-0-5/02(0)
PRINTED IN U.S.A.

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